ARCHSEL_STATUS

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Interpret as ARCHSEL_STATUS

CORE1=arm, CORE0=arm

Description

Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update.

Fields

CORE0	Current architecture for core 0. Updated on processor warm reset. 0 (arm): Core 0 is currently Arm (Cortex-M33) 1 (riscv): Core 0 is currently RISC-V (Hazard3)
CORE1	Current architecture for core 0. Updated on processor warm reset. 0 (arm): Core 1 is currently Arm (Cortex-M33) 1 (riscv): Core 1 is currently RISC-V (Hazard3)

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